The present invention relates generally to the fields of semiconductor devices and processing. More particularly, it concerns semiconductor devices, and processes for forming the same that include a conductor having a varying composition.
Polycrystalline silicon germanium alloy (SiGe) gate electrodes help reduce poly depletion effects in N- and P-MOSFETS. However, silicon germanium alloy is typically incompatible with certain silicide integrations. In particular, SiGe is incompatible with metal silicide integrations such as cobalt silicide integration or titanium silicide integration. In these cases, cobalt forms a high resistivity phase with underlying germanium or titanium to form, for instance, cobalt germanide (CoGe), cobalt digermanide (CoGe2), titanium germanide (TiGe), or titanium digermanide (TiGe2).
Further, germanium tends to segregate at the silicide/poly interface. This segregation may be disadvantageous in that germanium may be drawn away from the gate dielectric interface. This, in turn, may negatively affect the work function of the device; specifically, the work function may be increased.
In order to overcome such problems, a silicon layer may be formed on a silicon germanium alloy to provide a layer of silicon for silicidation. During the silicidation process, some of this silicon layer may be consumed. Although this technique has exhibited at least a degree of utility, problems nevertheless remain. In particular, germanium tends to diffuse into the silicon layer during each and every time-temperature cycle that is performed as a device is formed. This depletes the silicon germanium layer close to the dielectric and some of the benefit from the silicon germanium gate electrode (reduction in the poly depletion effect) may be lost. Even in the presence of this additional silicon layer, diffused germanium in the silicon layer may form CoGe2, CoGe, TiGe, and/or TiGe2 and adversely affect the gate silicide sheet resistance. Specifically, the sheet resistance may increase due to presence of these germanium compounds.
In one reference, a thin nitrided silicon film may be placed on top of a silicon layer. This nitrided silicon film may reduce the amount of up-diffusion from a gate level; however, because the nitrided silicon film is an insulating layer, that layer may negatively affect the performance of the device due to higher sheet resistance.
Problems enumerated above are not intended to be exhaustive, but rather are among many that tend to impair the effectiveness of previously known devices and techniques. Other noteworthy problems may also exist; however, those presented above should be sufficient to demonstrate that methodology appearing in the art have not been altogether satisfactory. In particular, existing techniques do not adequately account for and/or prevent up diffusion of certain elements that may have adverse affects on device performance and do not prevent the formation of performance-hampering compounds such as CoGe, CoGe2, TiGe, or TiGe2.